Recently, a semiconductor device manufacturing process has employed a dual damascene process in which a via contact and a wiring are simultaneously formed by filling a metal such as copper or the like into a via hole and a trench formed on a semiconductor substrate.
As for the aforementioned dual damascene process, there is known a method for forming a via contact and a wiring through following processes (see Japanese Patent Laid-open Application No. 2004-111950, for example). In such method, first of all, a via hole is formed by etching an insulating film with a via resist mask. Next, a residual resist mask is removed by ashing and, then, a protective film for protecting an underlayer disposed at the bottom of the via hole is formed by a chemical vapor deposition using a CVD or the like. Thereafter, a trench resist mask is formed by performing a photoresist coating process using a coater, an exposure process using an exposure device, a developing process using a developing apparatus or the like. Next, a wiring trench is formed by an etching process using the trench resist mask and, then, the residual resist mask, and the protective film are removed by an ashing process and an etching process or the like.
With the aforementioned processes, a via hole and a trench are formed and, then, a metal such as copper or the like is filled into the via hole and the trench by using a plating unit or the like. Thereafter, by polishing the surface with a chemical mechanical polishing (CMP) or the like, the metal on an area where the trench is not formed is removed to form a via contact and a wiring.
In the conventional method described above, however, an etching apparatus, a CVD apparatus, or an ashing apparatus is needed to execute a plurality of steps for performing a dual damascene process. Moreover, a semiconductor wafer may need to be cleaned in the steps, which results in an extended time of manufacturing process.